Phase Locked Loop (PLL) circuits are widely used to tune local oscillators in radio receivers. In a tunable phase locked loop circuit, a "divide by N" signal, which is derived from the output of a voltage controlled oscillator (VCO), is brought into phase lock with a reference frequency signal. The PLL circuit includes a phase detector circuit which compares the phase of the reference frequency signal and the "divide by N" signal and generates increase frequency and decrease frequency signals for selectively increasing and decreasing control voltage to the VCO. Although increase frequency and decrease frequency signals are generated at the reference frequency, loop stability considerations typically limit the closed loop bandwidth to a fraction of the reference frequency.
When the PLL circuit is "locked" to the reference frequency and there is little or no phase difference between the "divide by N" signal and the reference frequency signal, the phase detector must detect at least a minimum threshold phase difference before a significant decrease frequency signal or a significant increase frequency signal is generated. A significant signal is a signal of sufficient duration to keep the loop active. In the absence of significant signals, there is an effective "open loop" or "dead band" condition on the loop which allows the VCO to slowly and randomly drift up or down in output frequency. VCO drift in frequency is caused by random noise or leakage paths within the loop which may increase or decrease VCO operating frequency. The relatively slow variations in VCO output frequency, when in the "dead band" condition, adversely affect loop stability and result in unacceptable FM noise modulation of the VCO output signal.
Where the stray leakage paths are sufficient to maintain a static phase error beyond the phase detector threshold, the loop will not enter the dead band condition and correction increase frequency or decrease frequency signals will be generated correctly. In many prior art PLL circuits there are sufficient stray leakage paths to sustain activity on the loop at the reference frequency. If the stray leakage paths are not sufficient to sustain such loop activity, a resistor of high value can be added to provide an explicit leakage path.
In any event, prior art PLL circuits which rely on stray or intentional leakage exhibit undesirable performance. The VCO is subject to continuous phase pulling which is periodically brought back into alignment by the control signal (pulses) from the phase detector. This in turn produces a periodic ripple on the input signal to the VCO. The result is the introduction of side bands on the VCO occurring at multiples of the reference frequency. This condition is typically remedied by reducing the loop bandwidth and introducing additional low pass poles in the loop filter.
One prior art method of improving on the above described limitations of analog leakage is know as pulse injection.
Rather than using an analog leakage path, if the leakage is injected as a pulse, which is normally timed to correspond to the correction pulse from the phase detector, the spectrum generated by the injection pulse and the correction pulse (from the phase detector) essentially cancel each other. This reduces but does not eliminate completely side band noise.
It is desirable to have a phase locked loop circuit which has both predictable loop dynamics and low side band noise.